[HDLBits] Wire

Wire - HDLBits

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# 들어가며

HDLBits는 Verilog의 백준 같은 사이트이다. 여러가지 문제들이 있고, 그 문제를 직접 submit 할 수 있는 사이트이다. 혼자서 베릴로그를 공부하는 나에게는 굉장히 도움이 많이 되는 고마운 사이트이다.

 

코드를 submit 하고 나서는 다음과 같은 4개의 상태가 표시된다. 물론 Success를 받을 수 있도록 하는 것이 목표이다!

• Compile Error — Circuit did not compile.
• Simulation Error — Circuit compiled successfully, but simulation did not complete.
• Incorrect — Circuit compiled and simulated, but the outputs did not match the reference.
• Success! — Circuit was correct

# 문제

Create a module with one input and one output that behaves like a wire.

Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog "continuous assignment" (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is "continuous" because the assignment continues all the time even if the right side's value changes. A continuous assignment is not a one-time event.

 

The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.

 

The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. The module and port declarations create the black portions of the circuit. Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.

 

In addition to continuous assignments, Verilog has three other assignment types that are used in procedural blocks, two of which are synthesizable. We won't be using them until we start using procedural blocks.

Expected solution length: Around 1 line.

 

Wire처럼 행동하는 하나의 input과 하나의 output을 가지는 모듈을 생성하시오.

물리적 Wire과 다르게 Verilog에서의 Wire는 방향성이 있습니다. 즉, 데이터와 같은 정보들은 source에서 sink(sink는 driver이라고도 불리는데, 값들을 밖으로 drive 하기 때문입니다)로의 오직 한 방향으로만 움직인다는 것입니다.

Module Declaration

module top_module( input in, output out );

 

Baseline Code

module top_module( input in, output out );

endmodule

# 정답

module top_module( input in, output out );
    assign out = in;
endmodule

# 풀이

out wire에다가 in wire를 assign 하면 되는 문제였다. 굉장히 간단하지만, Verilog의 많은 내용들이 문제에 친절하게 설명되어 있다.